full buffer
英 [fʊl ˈbʌfə(r)]
美 [fʊl ˈbʌfər]
网络 全缓冲; 满队列; 缓冲溢出; 全驱动
双语例句
- This changes the state of the buffer to FULL.
这样就把缓冲的状态变成FULL。 - With this formatter now available, the second for loop can finally iterate through the full range of line numbers, retrieving the corresponding text buffer contents one line at a time
有了这个格式化程序后，第二个for循环就可以遍历完整的行号范围，每次取回一行相应的文本缓冲内容 - Because the state of the internal buffer is FULL, the available data is returned and a notify() issued.
因为内部缓冲的状态是FULL，所以可用数据将被返回，并发出一个notify（）。 - This allocation allows the thread to continue to run while a full trace buffer is written to the filesystem.
当一个跟踪缓冲区满了时，将它写到文件系统中，这使线程能够连续运行。 - Setup expanded the full path of a symbolic link and it overflowed the specified buffer.
安装程序在扩充符号链接完整路径时溢出指定的缓冲区。 - At the International Criminal Tribunal for the former Yugoslavia, war-crimes trials are screened in full, usually with a30-minute buffer so that sensitive statements can be blotted out.
在前南斯拉夫的国际刑事法庭，对战争罪的审判是全程拍摄的，并且通常保留了30分钟的缓冲时间以保证能消除敏感语句。 - When the producer thread production product, if the buffer is full, then the producer thread must wait for the release of the consumer thread to an empty buffer.
消费者线程从缓冲区中获得产品，然后释放缓冲区。当生产者线程生产产品时，如果缓冲区已满，那么生产者线程必须等待消费者线程释放出一个空缓冲区。 - It is a full symmetrically, current feedback amplifier followed by a diamond buffer that runs open loop.
这是一个完全对称，电流反馈放大器之后，钻石缓冲开环运行。 - Giving full play to the characteristic of large amount of on-chip memory, DSP acquires and processes the signal of linear CCD with the on-chip buffer alternately.
充分发挥DSP处理器片内存储器容量大的特点，使用其片内数据缓冲区交替对CCD进行信号采集和数据处理； - Simulation model for capture and buffer phase is built based on ADAMS software, in the model, capture ring is accurately built with full consideration of actual geometrical feature, buffer system is modeled the same as that of DDSS, and ADAMS impact model. Is adopted.
建立了捕获段与缓冲段的ADAMS仿真模型，其中对接机构采用精确的实体三维模型，缓冲力模型同上，接触力采用ADAMS软件提供的的Impact模型。 - Full Custom Design of the Branch Target Buffer for X Microprocessor
X微处理器BTB部件的全定制设计 - To determine the buffer capacity in the assembly system, based on the construction of the mathematical model of the buffer state, the probability of the buffer being full was determined as a function of buffer capacity according to the theory of stochastic process.
为了确定装配系统中的缓冲区容量，在建立缓冲区状态数学模型的基础上，根据随机过程的原理，提出了缓冲区被充满概率和缓冲区容量之间的函数关系。 - By reducing the TCP/ IP stack, we adopt full assembly programming method, flexible message control mechanism and buffer management, and realize a TCP/ IP stack in limited program space.
通过对TCP/IP协议进行裁减，采用全汇编语言程序设计方法、灵活的消息控制机制和缓冲区管理，在有限的代码空间内实现了TCP/IP协议栈。 - The dependence of emission spectra line intensity and electronic temperature and FWHM ( the full width half maximum) on the space and pressure of buffer gas are studied.
研究了原子发射谱线强度、电子温度和半高全宽（FWHM）随空间、缓冲气体压力变化的规律。 - The cavity full of high-press oil and the cavity for compensation can make the piston buffer well;
由高压下腔和补油油腔组成的缓冲系统较好地实现了活塞缓冲； - Then output traffic stream is converted into continuous time Markov Chain, the probability Characteristics of output traffic stream are analysed and the output queues length distribution and full buffer probability are obtained.
然后，将输出分组流转换为连续时间的马尔柯夫链，分析了输出分组流的概率特性，并得到了输出排队长分布和充满缓冲器的概率。 - The combination of these two methods, which can the use to the full of the GIS overlay analysis and buffer analysis, spatial analysis function and the ability to deal with attribute data, can effectively and objectively reflect the real extent of the quality of arable land.
这两种方法的结合，充分运用了GIS的叠置分析和缓冲分析等空间分析功能和处理属性数据的能力，能有效、客观的反映耕地质量的实际程度。 - For next general half palm and full palm product, will think of high capacity buffer 、 high speed transmission rate 、 living life detection and so on.
下一代半掌或全掌图像产品，将会考虑大容量数据缓存、高速传输、活体指纹检测等方面做进一步的研究。 - This is not conducive to the full buffer is not conducive to rapid kicking, but also to improve the speed at first jump harm than good.
这样既不利于充分缓冲，也不利于快速蹬伸，对提高腾起初速度也是弊远大于利。 - Because of the specialties of the IP design, driver designer should consider the route switch between the high-speed and the full speed controller, access to shared buffer, and the mode of ARM accessing the IP core as a slave.
由于IP硬件设计的特殊性，主机控制器驱动的设计需要考虑到高速与全速控制器的路由切换与缓存区的共享，以及ARM访问作为SLAVE的IP核的方式。